STA_L1i - Static Timing Analysis Introduction
STA_L1c Overview of VLSI Backend Design Flow
STA_S2_L1_Intro Session - Static Timing Analysis (Basic To Advance)
STA_L2h - Introduction to LIB File
STA_L1f - Overview of Floorplan Aware Synthesis
Physical Design Using Synopsys Tool - Intro Session - Batch 2023
VLSI Expert - Student's View : Madhuparna
Lecture-1 Introduction to System Verilog Register, Wire datatypes
Session on "Basic Low Power concepts" By Kavita Mehta