PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
PD Lec 66 - Routing Concepts | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 25 - Physical Only Cells | Floor-planning | VLSI | Physical Design
PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 48-Interview Questions | placement | VLSI | Physical Design
PD Lec 30 - Interview Questions | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design
x64 Assembly and C++ Tutorial 67: SSE Min and Max Instructions
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
Insertion delay/ Propagation delay
