PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 66 - Routing Concepts | VLSI | Physical Design
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 33 - Placement and Optimization | VLSI | Physical Design
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design
PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
PD Lec 35 - Scan Chain Optimization | VLSI | Physical Design
![PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design](https://img.youtube.com/vi/AW6OwZxY7VY/0.jpg)
![PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design](https://img.youtube.com/vi/Z1Cxbn5LOYg/0.jpg)
