PD Lec 62 - CTS Analysis | VLSI | Physical Design
Lec 62 Compensator & Controller (Contd.)
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
PD Lec 10 - LEF File | PD Inputs part-4 | VLSI | Physical Design
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
Lec 62 Carcinoma Breast Immunohistochemistry Classificaiton || Breast
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
