PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 9 - Timing Library | libs | PD Inputs part-3 | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
PD Lec 26 - Sanity Checks -1 | Floor-planning | VLSI | Physical Design
PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design
PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 66 - Routing Concepts | VLSI | Physical Design
![PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design](https://img.youtube.com/vi/Z1Cxbn5LOYg/0.jpg)
