PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design
PD Lec 41 - Tie Cell | tie low| tie high | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
Lec 60 GATE Problem on Compensator
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 9 - Timing Library | libs | PD Inputs part-3 | VLSI | Physical Design
![PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design](https://img.youtube.com/vi/Z1Cxbn5LOYg/0.jpg)
