PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 11 - Constraints File | PD Inputs part-4 | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
PD Lec 22- Blockages and Keep-out Margin | Floor-planning | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
