PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PD Lec 31 - Introduction to Placement | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
