PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
Lec 42: Analysis and Head-Discharge curve of PD pump
PD Lec 41 - Tie Cell | tie low| tie high | VLSI | Physical Design
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PhD - I Won't Let You Down (HQ)
PD Lec 22- Blockages and Keep-out Margin | Floor-planning | VLSI | Physical Design
Chronic Kidney Disease (CKD) | Clinical Medicine
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
PD Lec 32 - Placement of std cells | VLSI | Physical Design
sta lec22 timing exceptions part 1 | false path | Static Timing Analysis tutorial | VLSI
