PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
PD Lec 66 - Routing Concepts | VLSI | Physical Design
PD Lec 39 - CMOS Latch Up | VLSI | Physical Design
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
PD Lec 62 - CTS Analysis | VLSI | Physical Design
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
PD Lec 23 - Macro placement issues | | Floor-planning | VLSI | Physical Design
PD Lec 40 - Well Tap Cell | VLSI | Physical Design
PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design
PD Lec 37 - Pin Density of std cells | VLSI | Physical Design
PD Lec 41 - Tie Cell | tie low| tie high | VLSI | Physical Design
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
Understanding Peripheral Arterial Disease
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
PD Lec 3 - CMOS Basics part-2 | Tutorial | VLSI | Physical Design
PD Lec 31 - Introduction to Placement | VLSI | Physical Design
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
PD Lec 6 - CMOS basics part 4 | Tutorial | VLSI | Physical Design
Full process of Tendering & Contracts with all terminologies from start to end - Explained |
Lec 38 CS: Introduction to P, PI and PID controller
