FPGA/SoC + DDR PCB Design Tips - Phil's Lab #59
BGA PCB Design Tips - Phil's Lab #95
Interfacing FPGAs with DDR Memory - Phil's Lab #115
FPGA + PCIe Hardware Accelerator Design Walkthrough (DDR3, M.2, ..) - Phil's Lab #82
FPGA & SoC Hardware Design - Xilinx Zynq - Schematic Overview - Phil's Lab #50
FPGA/SoC Board Bring-Up - DDR3 (Zynq Part 2) - Phil's Lab #97
PCB High-Speed Delay Matching - Phil's Lab #110
FPGA PCB Design Review - Phil's Lab #85
LPDDR4 PCB Design and Layout Tutorial - LPDDR4 Length Matching
How to Do DDR Memory Bit & Byte Swapping - DDR2, DDR3, DDR4, ....
FPGA/SoC Board Bring-Up Tutorial (Zynq Part 1) - Phil's Lab #96
FPGA and BGA PCB Power Delivery Best Practices
Your BGA and You | PCB Layout
FPGA Pins Explained!
High-Speed PCB Design Tips - Phil's Lab #25
PCB design best practices: FPGA/PCB co-design
Understanding fanout and breakout on DDR4 chips | PCB design flow series: Chapter 3.2
How To Improve Your PCB Designs (Common Mistakes) - Phil's Lab #18
High Density Interconnect - Addressing Complex and Dense PCB Designs
How to do BGA fanout - VIAs & Layers
