CombCkt-5 - Gate Delay
CombCkt - 5 - Gate Delay
CombCkt - 4 - Logic Gate Capacitance
CombCkt - 3 - Gate Sizing
CombCkt-4 - Logic Gate Capacitance
CombCkt - 16 - Pseudo NMOS Inverter
CombCkt - 10 - Path Delay Calculation and Optimization Formulation
CombCkt - 15 - Pseudo NMOS Logic
CombCkt - 7 - Gate Delay with a Load Capacitance
CombCkt - 13 - Skewed Gates
CombCkt-21 - Gate Sizing for Large Circuits
CombCkt - 11 - Buffer Insertion
CombCkt - 8 - Logical Effort
CombCkt - 1 - Implementing Any Boolean Logic Function
CombCkt - 14 - Special Functions
CombCkt - 12 - Input Ordering and Asymmetric Gates
CombCkt-17 - Pseudo NMOS Logical Effort and CVSL
CombCkt-2 - Implementing Any Boolean Logic Function: Examples. Gate sizing
CombCkt - 10B - Path Delay Optimization: Example
CombCkt - 18 - Dynamic Circuits and Input Monotonicity