Zephyr RTOS for RISC V and FPGA - Manojkumar Subramaniam
Bring Multicore RISC-V and Zephyr RTOS Together
Zephyr And RISC-V: I Aint Afraid of No Ghosts (FOSDEM 24)
SERV RISC-V Core on Kiwi-1P5 FPGA: Hello from Zephyr RTOS
Lightning Talk: The CFU: Custom Hardware with RISCV and Zephyr - Mohammed Billoo, MAB Labs Embedd...
Integrating RISC-V PMP Support in Zephyr
Automated, Simulation-Based Flow for Low-Cost FPGA-Accelerated Devices with Zeph... Piotr Zierhoffer
The Harsh Truth about FPGAs (You Should Avoid Them?!)
Zephyr RTOS on Reconfigurable Platforms – State of the Art // Zephyr Meetup Garching, Sept. 18, 2025
Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology
Mini-conference: RISC-V Support in Zephyr
Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr TensorFlow, and Renode
Running FreeRTOS on RISC-V RV32I (FPGA implementation)
What Work Is Zephyr Doing To Support RISC-V ISA
How Antmicro Is Bringing Zephyr And FPGAs Closer
Build Zephyr for MicroBlaze-V FPGA Using Yocto Project - Sandeep Gundlupet Raju, AMD
Live Demo: Setting Up Espressif RISC-V with Zephyr & Golioth | Embedded Linux Conference
LDC24 Demo - MosChip Company Opensource RISC-V Core Running Zephyr RTOS on Various Lattice FPGAs
Antmicro at Embedded World 2020, FPGA, edge to cloud AI, RISC-V open hardware and software, Renode
RISC-V Linux in litex/Rocket CPU on FPGA ArtyA7 build Gateware