Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology
Lightning Talk: The CFU: Custom Hardware with RISCV and Zephyr - Mohammed Billoo, MAB Labs Embedd...
Mini-conference: RISC-V Support in Zephyr
Multi-core Application Development with Zephyr RTOS - Alexey Brodkin, Synopsys
Zephyr RTOS for RISC V and FPGA - Manojkumar Subramaniam
Integrating RISC-V PMP Support in Zephyr
What Work Is Zephyr Doing To Support RISC-V ISA
Safety + SBOMs + Zephyr RTOS - Kate Stewart, The Linux Foundation
Asymmetric/Heterogeneous MultiProcessing (AMP/HMP): Mainline Linux and Zephyr in... Marcel Ziswiler
RISC-V and Functional Safety - Florian Wohlrab, Andes Technology
How I Fell in Love with Zephyr – a System Architect’s Tale - Tobias Kästner & Stephan Linz
Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc.
Zephyr Mini Summit
FSW 2022: RISC-V soft-core processors for spaceflight embedded platforms
RVfpga: Using A Commercial RISC-V Processor to Teac... - Sarah L. Harris & Daniel A. Chaver Martinez
CompSoc AGM 2022
Dual-Core RISC-V system on FPGA
Extending the RISC-V ISA for Optimized Support of CNNs in a Multi Core Context
Going West: How We Develop and Maintain a Zephyr-based Microcontroller SDK - Carles Cufí
Zephyr OS BLE controller conformance testing